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optimize(infer): move modules into rvc
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@@ -79,7 +79,6 @@ class SynthesizerTrnMsNSFsidM(nn.Module):
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upsample_kernel_sizes,
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gin_channels=gin_channels,
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sr=sr,
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is_half=kwargs["is_half"],
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)
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self.enc_q = PosteriorEncoder(
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spec_channels,
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