From 0b3e695ecc77a334fafe30ee36de504c41ec4d6a Mon Sep 17 00:00:00 2001
From: Harshavardhana <harsha@harshavardhana.net>
Date: Tue, 28 Jun 2016 02:55:56 -0700
Subject: [PATCH] Add travis build CI.

---
 .travis.yml       | 21 +++++++++++++++++++++
 compress_amd64.go | 11 ++++++-----
 compress_amd64.s  |  5 ++---
 3 files changed, 29 insertions(+), 8 deletions(-)
 create mode 100644 .travis.yml

diff --git a/.travis.yml b/.travis.yml
new file mode 100644
index 0000000..545066e
--- /dev/null
+++ b/.travis.yml
@@ -0,0 +1,21 @@
+sudo: required
+dist: trusty
+language: go
+
+os:
+- linux
+- osx
+
+osx_image: xcode7.2
+
+go:
+- 1.6
+- 1.5
+
+env:
+- ARCH=x86_64
+- ARCH=i686
+
+script:
+- diff -au <(gofmt -d .) <(printf "")
+- go test -race -v ./...
diff --git a/compress_amd64.go b/compress_amd64.go
index ba569e5..0a5299e 100644
--- a/compress_amd64.go
+++ b/compress_amd64.go
@@ -20,9 +20,9 @@
 package blake2b
 
 //go:noescape
-func blockSSE(p []uint8, in, iv, t, f, shffle, out []uint64)
+func blockAVX(p []uint8, in, iv, t, f, shffle, out []uint64)
 
-func compressSSE(d *digest, p []uint8) {
+func compressAVX(d *digest, p []uint8) {
 	h0, h1, h2, h3, h4, h5, h6, h7 := d.h[0], d.h[1], d.h[2], d.h[3], d.h[4], d.h[5], d.h[6], d.h[7]
 
 	in := make([]uint64, 8, 8)
@@ -42,7 +42,7 @@ func compressSSE(d *digest, p []uint8) {
 
 		in[0], in[1], in[2], in[3], in[4], in[5], in[6], in[7] = h0, h1, h2, h3, h4, h5, h6, h7
 
-		blockSSE(p, in, iv[:], d.t[:], d.f[:], shffle, out)
+		blockAVX(p, in, iv[:], d.t[:], d.f[:], shffle, out)
 
 		h0, h1, h2, h3, h4, h5, h6, h7 = out[0], out[1], out[2], out[3], out[4], out[5], out[6], out[7]
 
@@ -53,9 +53,10 @@ func compressSSE(d *digest, p []uint8) {
 }
 
 func compress(d *digest, p []uint8) {
+	// Verifies if AVX is available, use optimized code path.
 	if avx {
-		compressSSE(d, p)
+		compressAVX(d, p)
 		return
-	}
+	} // else { fallback to generic approach.
 	compressGeneric(d, p)
 }
diff --git a/compress_amd64.s b/compress_amd64.s
index 18ca7ba..beb1429 100644
--- a/compress_amd64.s
+++ b/compress_amd64.s
@@ -120,9 +120,8 @@
     MOVOU  0(SI), X12           // X12 = 03040506 07000102 0b0c0d0e 0f08090a
 
 
-// func blockSSE(p []uint8, in, iv, t, f, shffle, out []uint64)
-TEXT ·blockSSE(SB), 7, $0
-
+// func blockAVX(p []uint8, in, iv, t, f, shffle, out []uint64)
+TEXT ·blockAVX(SB), 7, $0
     // REGISTER USE
     //  X0 -  X7: v0 - v15
     //  X8 - X11: m[0] - m[7]